Want to know the three lessons for GLOBALFOUNDRIES from its 28nm high-K, metal-gate development?
September 1, 2011
Yesterday, I attended the Global Technology Conference, a chip-making extravaganza underwritten by GLOBALFOUNDRIES and its partners. Got several blog posts to write about this information-packed day but thought I’d start with the three lessons that GLOBALFOUNDRIES learned from its 28nm high-K, metal-gate development, as told by Gregg Bartlett, Senior VP of Technology and Engineering at GLOBALFOUNDRIES.
Here are the lessons:
To read the full article, click here
Related Semiconductor IP
Related Blogs
- 28nm Ramp Starts At Globalfoundries
- Globalfoundries 22FDX Technology Shows Advantages in PPA over 28nm Node
- 28nm-SLP technology - The Superior Low Power, GHz Class Mobile Solution
- UMC versus GLOBALFOUNDRIES
Latest Blogs
- Designing for What Comes Next in AI
- Secure boot on Efinix Titanium Ti60: Getting started with KiviBoot-Tiny
- How Long Does It Take to Port a New AI Model? Minutes Now, and Falling
- PCI Express Security and TEE Integration, Part 1 - Establishing Trust
- World Models at the Edge, in Real Time: V-JEPA 2.1 on the Quadric GPNPU