Formal verification best practices: investigating a deadlock
September 26, 2023
In our first episode from last week we focused on best practices when setting up formal verification on a component. Our setup is now ready with protocol checkers to avoid unrealistic scenarios (which also helped find a new bug), and with basic abstractions to improve performances. It’s now time to tackle our real task: reproducing a deadlock bug found using simulation. Let’s dive deep into it.
Reproducing the deadlock bug
To ensure a design is deadlock free, one approach consists in verifying that it is “always eventually” able to respond to a request. The wording is important. Regardless of the current state and the number of cycles we must wait, in the future the design must respond.
To read the full article, click here
Related Semiconductor IP
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
- Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
- Performance P570 Gen 3
Related Blogs
- Formal verification best practices to reach your targets
- Formal verification best practices: towards end-to-end properties
- Formal verification best practices: checking data corruption
- Formal verification best practices: sign-off and wrap-up
Latest Blogs
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA
- Beyond PCIe Compliance: Why Stress Testing Is Crucial for Edge AI Deployments