Exploring & Characterizing DDR Memory System Margins
Memories are central to system operation and performance. Designers need a better way to look inside the memory subsystem to ensure the system is optimized for production.
Memories are hot. At least that's what one would surmise from the recent MemCon 2014 in Santa Clara, Calif., where the exhibit floor was crowded and a full day of presentations covered all things memory.
One recurring theme at the conference was whether there is a more efficient way to explore and characterize the margins of a DDR memory subsystem. That's not so easy when the DDR subsystem (DDR controller, PHY and I/O) is embedded within a chip and is responsible for managing the data traffic flowing to and from the processor and external DDR memory. The DDR memory interface normally is the highest bandwidth bus in the system, operating at multi-GHz data rates with read-write timing margins measured in picoseconds.
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