New AXI Scatter-Gather DMA Core Transfers Streaming Data to/from System Memory
Data processing accelerators are often designed with streaming interfaces and are meant for continuous flow through a custom hardware processing pipeline. Such cores include engines for compression, cryptography, or packet processing. A custom hardware pipeline built of such cores would be similar to this:
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Sometimes, though, designers want the data processing accelerator to store or retrieve its data to or from the systems memory rather than directly transferring data to or from the next or preceding pipeline stage. So, our example custom hardware pipeline now transforms to something like this:

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