Vendor: SmartDV Category: DDR

DDR Synthesizable Transactor

DDR Synthesizable Transactor provides a smart way to verify the DDR component of a SOC or a ASIC in Emulator or FPGA platform.

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Overview

DDR Synthesizable Transactor provides a smart way to verify the DDR component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR Synthesizable Transactor is fully compliant with standard JESD79F Specification and provides the following features.

Key features

  • Supports 100% of DDR protocol standard JESD79F
  • Supports all the DDR commands as per the specs
  • Supports all device speeds as per specification
  • Supports programmable CAS latency
  • Supports programmable burst lengths: 2,4 and 8
  • Supports write data mask
  • Supports the following devices:
    • X4
    • X8
    • X16
  • Supports up to 1 GB device density
  • Supports the following burst types:
    • Sequential
    • Interleave
  • Supports burst order
  • Supports all mode register programming
  • Supports extended mode register programming
  • Supports auto refresh & self-refresh modes
  • Supports auto precharge option for each burst access
  • Supports power down features
  • Supports DLL operation
  • Checks for following:
    • Check-points include power up, initialization and power off rules
    • State based rules, active Command rules
    • Read/Write command rules etc
    • All timing violations
  • Bus-accurate timing for min, max and typical values
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

DDR Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the DDR testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
DDR Transactor
Vendor
SmartDV
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about DDR IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about DDR Interface IP

What is DDR Synthesizable Transactor?

DDR Synthesizable Transactor is a DDR IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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