Europe Needs Volume FD-SOI Fab To Meet Kroes' 20% Target
January 27, 2014
The cornerstone of the European Leaders Group (ELG) report to Neelie Kroes, due in a week or two, should be the construction of a high volume FD-SOI wafer fab, said Malcolm Penn, CEO of Future Horizons, at the company’s forecast meeting in London, earlier this week.
The ELG was set up to devise a plan to implement the 20% European semiconductor market share target in Kroes’ 10/100/20 plan.
The ELG was due to report on December 16th. But instead of a detailed roadmap the EC issued a statement of general aspirations with an undertaking that a detailed roadmap for implementation would be published in late January or early February.
To read the full article, click here
Related Semiconductor IP
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
Related Blogs
- Fab For Europe
- Is European Fab Feasible?
- Have EC And ST Changed Tack On European Fab?
- Support For European 450mm Fab Strengthening
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car