Designing Chips in the Cloud: Four Key Takeaways from SNUG Silicon Valley 2023
In recent years, many semiconductor companies have successfully shifted chip design from on-premises data centers to the cloud. With monolithic systems on chips (SoCs) and multi-die systems becoming ever-more complex, chip designers increasingly rely on “unlimited” cloud resources and new cloud-native, AI-driven EDA tools to rapidly optimize power, performance, and area (PPA).
Unsurprisingly, cloud-based chip design was the subject of numerous sessions and tracks at the Synopsys Users Group (SNUG) Silicon Valley 2023 conference, including a panel titled “Harnessing the Power of the Cloud: Is the Ecosystem Ready?” During the session, industry experts identified the following four trends driving the rapid migration of EDA tools and chip design workloads to the cloud:
- Ever-increasing compute demands
- Accelerated time-to-market requirements
- Evolving cyber threats and stringent security protocols
- A growing need for more flexible, cost-effective storage options
Read on to learn about key takeaways from the panel experts—and get an in-depth look at how cloud-native EDA tools and pre-optimized hardware platforms are empowering semiconductor companies to accelerate their chip design cycles.
To read the full article, click here
Related Semiconductor IP
- DFI 6.0 Verification IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
Related Blogs
- Implementing Dual-core Lockstep in the CHIPS Alliance VeeR EL2 RISC-V core for safety-critical applications
- Implementing I3C Host Controller support in the open source I3C Core
- Analog Design and Layout Migration automation in the AI era
- The Hidden Threat in Analog IC Migration: Why Electromigration rules can make or break your next tapeout