Delivering Terabyte-Scale Bandwidth with HBM3-Ready Memory Subsystem
An exponential rise in data volume, and the meteoric rise of advanced workloads like AI/ML training, requires constant innovation in all aspects of computing. Memory bandwidth is a critical enabler of unleashing the power of processors and accelerators, and the High Bandwidth Memory (HBM) standard has evolved rapidly to deliver the performance required by the most demanding applications.
For current generation HBM2E, Rambus introduced the industry’s fastest memory subsystem capable of 4 gigabits per second (Gbps) operation. With a 1024-bit wide interface, 4 Gbps signaling delivers 512 gigabytes per second (GB/s) of bandwidth. In accelerator architectures with 4-6 HBM2E DRAM devices (each device being a 3D stack of DRAM chips), there’s the capability for 2-3 Terabytes per second (TB/s) of memory bandwidth. That’s enormous, but the appetite for bandwidth is insatiable, so the wheel of innovation needs to keep spinning.
To read the full article, click here
Related Semiconductor IP
- HBM3 PHY and Controller.
- HBM3 Memory Model
- HBM3 DFI Verification IP
- HBM3 Synthesizable Transactor
- HBM3 Controller IIP
Related Blogs
- Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces
- Qualcomm JEDEC Mobile Keynote: Memory Bandwidth and Thermal Limits
- It's about the mobile GPU memory bandwidth per watt, folks
- PCI Express: Delivering Needed Bandwidth for Open Compute Project
Latest Blogs
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car
- Reprogrammable Post-Quantum Security for SoCs: Why Crypto-Agility Matters
- Designing the Beam Steering Core for a C-Band AESA: A Look at VSI's VBF0644 GaAs Beamformer IC
- Secure Boot for embedded systems: Building a complete chain of trust