Challenges in chip integration

By EETimes

July 10, 2012

Chip integration is where all of the pieces for a new chip come together. In an ideal world, all of those pieces get done on time, they all go in one batch to the chip group responsible for the integration, who combines them all together in perfect harmony, pushes the button, and voilà!, off the full chip goes to the foundry, where it manufactures perfectly and performs exactly as it should.

Of course, the real world is more complicated, and that “waterfall” type of project is giving way more and more often to more “agile” or “concurrent” projects, where different blocks are on different development schedules and encounter different production issues, so the chip assembly is repeated over and over as pieces are completed or updated. This process requires compiling inputs from multiple groups, feeding back information on the results of the integration, and then managing updates and adjustments from each of those input streams, all while managing and controlling the overall delivery schedule. In addition to the obvious challenges of managing multiple datastreams, significant technical challenges must also be satisfied to ensure the integrity of those data, as well as maximize overall process efficiency.

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