Cadence's NVM Express: fruit from subsystem IP based strategy
July 4, 2012
If we look at SoC design evolution, we have certainly successfully passed several steps: from transistor by transistor IC design using Calma up to design methodology based on the integration of 500K + gates IP like PCIe gen-3 Controller, one out of several dozens of IP integrated in today’ SoC for Set-Top-Box or Wireless Application Processor. Are we naïve if we think the next step should be subsystem IP? It would really make sense to use an IP aggregation, organized in such a way that it could support a specific application!
To read the full article, click here
Related Semiconductor IP
- NVM Express (NVMe) Controller (compliant with NVMe 1.4 Base Specification)
- Universal NVM Express Controller (UNEX)
Related Blogs
- Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem
- The Next-Generation UCIe IP Subsystem for Advanced Package Designs
- Cadence Tapes Out 32GT/s UCIe IP Subsystem on Samsung 4nm Technology
- NVMe 2.0 Specifications: Support for Fabrics and Multi-Domain Subsystems
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions