Cadence's NVM Express: fruit from subsystem IP based strategy
July 4, 2012
If we look at SoC design evolution, we have certainly successfully passed several steps: from transistor by transistor IC design using Calma up to design methodology based on the integration of 500K + gates IP like PCIe gen-3 Controller, one out of several dozens of IP integrated in today’ SoC for Set-Top-Box or Wireless Application Processor. Are we naïve if we think the next step should be subsystem IP? It would really make sense to use an IP aggregation, organized in such a way that it could support a specific application!
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Related Semiconductor IP
- Universal NVM Express Controller (UNEX)
- NVM Express (NVMe) Controller (compliant with NVMe 1.4 Base Specification)
- NVMe Controller
- NVMe Host Controller
- High Performance NVMe for PCIe-based storage
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