LPDDR4 Memory Model

LPDDR4 Memory Model provides an smart way to verify the LPDDR4 component of a SOC or a ASIC. The SmartDV's LPDDR4 memory model is fully compliant with standard LPDDR4 Specification and provides the following features. Better than Denali Memory Models.

LPDDR4 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR4 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports LPDDR4 memory devices from all leading vendors.
• Supports 100% of LPDDR4 protocol standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C, JESD209-4D, JESD209-4X and LPDDR4Y (Proposed).
• Supports all the LPDDR4 commands as per the specs.
• Supports up to 32 GB device density.
• Supports the following devices.
• X8
• X16
• Supports all data rates as per specification.
• Quickly validates the implementation of the LPDDR4 standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C, JESD209-4D, JESD209-4X and JESD209-4Y (Proposed).
• Supports programmable clock frequency of operation.
• Support for all mode register programming.
• Supports for Programmable READ/WRITE Latency timings.
• Supports for both 16 and 32 Programmable burst lengths.
• Supports for Burst sequence.
• Checks for following
• Check-points include power up, initialization and power off rules,
• State based rules, Active Command rules,
• Read/Write Command rules etc.
• All timing violations.
• Supports for Write data mask and data strobe features.
• Supports for Write and Read DBI.
• Supports for Write leveling.
• Supports for CA training and DQ Vref training.
• Supports for ODT (On-Die Termination) features.
• Supports for ZQ/DQ Calibration commands.
• Supports for Byte mode.
• Supports for Single-ended mode.
• Supports for Power Down features.
• Supports for Self refresh.
• Supports for Refresh management.
• Supports Multi rank.
• Supports for input clock stop and frequency change.
• Supports for all types of timing and protocol violation detection.
• Supports for full-timing as well as behavioral versions in one model.
• Supports for all timing delay ranges in one model: min, typical and max.
• Protocol checker fully compliant with LPDDR4 Specification JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C, JESD209-4D, JESD209-4X and LPDDR4Y (Proposed).
• Constantly monitors LPDDR4 behavior during simulation.
• Supports for on the fly in burst lengths.
• Models, detects and notifies the test bench of significant events such as transactions, warnings, and timing and protocol violations.
• Built in functional coverage analysis.
• Supports Callbacks, so that user can access the data observed by monitor.

• Faster testbench development and more complete verification of LPDDR4 designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the LPDDR4 testcases.
• Complete UVM/OVM sequence library for LPDDR4 controller.
• Examples showing how to connect and usage of Model.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.