Beginners Guide To Clock Data Recovery
If you are new to the world of design and verification, you probably have a LOT of questions! One of them may pertain to an important element – the Clock Data Recovery. In this blog, we try and de-mystify this process.
The purpose of designing various protocols is to transfer a set of information (data) from one place to another. Often times, serial data communication is used to transmit the data at a high speed. At the receiver end, the transmitted data has to be retrieved without losing its integrity with the accompanied timing information. This process is called Clock and Data recovery.
In this blog, we are going to elaborate requirement of CDR and how CDR works, how to tackle with issues like jitter and PPM in modeling the CDR.
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