Axiomise: Formal, Especially for RISC-V
December 7, 2022
I recently talked to Ashish Darbari, the CEO of Axiomise. They are based in London, where Ashish ended up having bounced around the world. But more of that later. I also discovered that he would be presenting at CadenceLIVE In Munich the following week, so I planned to attend that presentation and discuss that in this post too.
If you've never heard of Axiomise, let me tell you what they do. They have a four-pronged approach to the market.
To read the full article, click here
Related Semiconductor IP
- RISC-V Display Connectivity Subsystem (DCS)
- RISC-V IOPMP IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
Related Blogs
- Raising RISC-V processor quality with formal verification
- How to Speed Up Simulation Coverage Closure with Formal Verification Tools
- Improving RISC-V Processor Quality with Verification Standards and Advanced Methodologies
- Synopsys TileLink Interconnect Verification IP for RISC-V SoCs
Latest Blogs
- A Repeatable Framework for Hardware Security Assurance
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA