Arm Cortex-A78AE: On the Road to an Autonomous Future

By Arm Ltd

October 1, 2020

It was a little less than 2 years ago that we announced the Cortex-A76AE processor as Arm’s first dedicated high-end CPU design for safety applications. In the time since, both the industry and Arm have come a long way. Autonomous class technologies are making rapid inroads into the automotive sector while demanding that security and functional safety requirements continue to be met. Equally, the application space has enlarged exponentially introducing pitstops on the way to the promised land of fully autonomous machines. Self valet-parking, on-ramp-to-off-ramp auto driving are realities (or close to being so) but of particular significance is the application of the underlying technologies in segments such as industrial warehousing and autonomous manufacturing. Clearly the twin demands of high performance compute and demonstrable safety are of great interest to a variety of market segments.

Our newest member of the AE family of CPUs, the Cortex-A78AE, comes just in time to service our partners’ ever-growing need for safe compute. Functional safety is evolving into an era of mixed-safety criticality underwritten by the move to domain controllers in automotive E/E architectures. The co-location of multiple application threads on a common software entity poses some interesting challenges in terms of thread management, responsiveness, and switching times between applications. On the industrial side, the deployment of common-off-the-shelf infrastructure for IT and the connecting of the OT (operational technologies) domain to the network raises concerns of security and guaranteed cycle times. A common thread running through all these themes is a desire for ever-increasing single thread compute performance. Equally, both the automotive and industrial segments are increasingly running into the thermal wall where deployable solutions are limited by the power dissipation limits of the system. Lastly, the dynamics of the industry dictate that the logic of reuse is maximized wherever feasible, particularly given the costs of chip design in the newer process geometries. This is especially true for partners who service multiple market segments. The bottom line is that the industry needs an uplift in safe, secure, single-thread compute performance that comes with improved power efficiency levels.