A Confident ASIC Design Path through Co-Creation
The first blog in this series talked about the competitive benefits to differentiating OEM products in hardware as well as software, followed by a high-level view of our co-creation programs. In this blog I would like to talk a bit more about the way we at CEVA and Intrinsix approach collaboration with OEM and semiconductor, for a confident path to turnkey ASIC design or to wireless subsystem design. To illustrate, imagine the kind of SoC you might want to build for a wireless smart speaker or smart home entertainment system. Core to this system is an audio pipeline supporting voice processing for control commands and wireless connectivity through Wi-Fi and Bluetooth connectivity, where the BT connection could be for remote control or audio streaming. We also include on-chip RF for Bluetooth and WiFi. An overall block diagram is shown below.
To read the full article, click here
Related Semiconductor IP
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
Related Blogs
- Cadence Generative AI Solution: A Comprehensive Suite for Chip-to-System Design
- Reducing design cycle time for semiconductor startups: The path from MVP to commercial viability
- How to Design a RISC-V Space Microprocessor
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car