5 things I will remember from the 2022 RISC-V Summit
December 22, 2022
After an intense week at the 2022 RISC-V Summit in San Jose, California, and a long journey back to Munich (30 hours!) I am back at our Codasip headquarters, fueled with energy and positive thoughts. I obviously had plenty of time in transit to reflect on the event which, once again, was unique in many ways. A lot happened in a few days for us at Codasip as well as for the wider RISC-V community, and here are 5 things I will remember from this conference.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related Blogs
- 5 good things about RISC-V
- AI is stress-testing processor architectures and RISC-V fits the moment
- Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain
- The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing