PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
For high-bandwidth applications, the PCIe 4.0 PHY IP delivers high-performance, multi-lane capabilities and a low-power design.
PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm
The high-bandwidth applications benefit from the low power, multi-lane, and high-performance PCIe 4.0 PHY IP's design.
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
With compatibility for PIPE 4.4 interface protocol, this Peripheral Component Interconnect Express (PCIe) x4 PHY complies with PC…
PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
With compliance for PIPE 4.4 interface spec, Peripheral Component Interconnect Express (PCIe) Gen4 PHY IP complies with PCIe 4.0 …
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE 4…
PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen4 SERDES PHY on Samsung 7LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen4 / Ethernet SERDES on TSMC CLN5
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
R-Tile is a FPGA companion tile that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction…
16G Multiproocol Serdes IP, Silicon Proven in TSMC 28HPC+
The multi protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 4.0, 3.0, 2.0 Base …
PCIe is the most common protocol in high speed serial standards to connect components in embedded systems.
PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 5.0 Base Specification with support of PIPE 5…
PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
The 16G Multi-Link and Multi-Protocol PHY is a silicon-proven, high-end SerDes operating at speeds from 1.25Gbps to 16Gbps featur…
The PCIe Gen 5 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 5 interfa…
Used by all PCIe, IP, and SoC design verification teams for all generations.The Cadence® Verification IP (VIP) for PCI Express® (…
16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provid…
The PCI Express® (PCIe®) 6.1 Controller with AXI is configurable and scalable controller IP designed for ASIC implementation.
The PCI Express® (PCIe®) 6.1 Controller is configurable and scalable controller IP designed for ASIC implementation.
Truechip's CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of a…