DDR DLL PHY IP Listing

DDR2 SDRAM Controller

• DDR
• now
• Supports industrial standar…

The DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3, DDR3L (1.3…

• Single-Protocol PHY

The DDR multiPHYs are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 S…

• Single-Protocol PHY
• Silicon Proven
• Immediate

This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solut…

• SPI / QSPI XSPI

The DDR4/3 PHY is compatible with JEDEC DDR3 and JEDEC DDR4 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to 2133Mbps…

• UMC
• 28nm
• HPC
• In Production

IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.

• PHY
• TSMC
• 3nm
• N3FFP
• Silicon Proven

The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to1866Mbps …

• UMC
• 40nm
• LP
• In Production

The AR531S13 is a low-jitter low power dual channel delay locked loop (DLL) design support for DDR application.

• SMIC
• 130nm
• G

The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA Intellectual Property (IP) provides simplified interfaces to industry…

• DDR

DisplayPort and HDMI Transmit technologies are complex mixed signal designs which require both high performance analog design (eq…

• Displayport
• Now