The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
- CXL
- In production
- Available
- CXL, PCI-SIG
The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
CXL 2.0 Integrity and Data Encryption Security Module
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge + LTI and MSI-GIC interfaces
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Controller IP for CXL addresses…
The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 3.0 Premium Controller EP/RP/DM 1024b/512b/256b/128b with AMBA bridge for CXL.io
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 3.0 Premium Controller EP/RP/DM 1024b/512b/256b/128b
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
Adds security Interfaces, features to CXL 3.0 Premium controllers
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL (Compute eXpress Link) 3.1 IP
The Panmnesia Compute Express Link (CXL) IP implements all necessary logic for CXL device, host, and switch.
PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet
Most PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express®…
Compliant with CXL Specification 2.0