Synopsys ARC Functional Safety (FS) Processor IP supports ASIL B and ASIL D safety levels to simplify safety-critical automotive …
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Synopsys ARC Functional Safety (FS) Processor IP supports ASIL B and ASIL D safety levels to simplify safety-critical automotive …
The new Synopsys ARC® NPX Neural Processing Unit (NPU) IP family delivers the industry’s highest performance and support for the …
The Synopsys ARC® SEM Family of performance-efficient, ultra-low power, compact security processors enables designers to integrat…
The Synopsys ARC® VPX DSP Family is optimized for the unique power, performance and area (PPA) requirements of embedded workloads…
Machine vision and deep learning are being embedded in integrated SoCs and expanding into high-volume applications such as automo…
Synopsys offers a suite of development tools, ARC development systems and operating systems, providing everything a developer nee…
Synopsys has a long history of working with DSP customers to meet the ever-increasing computation requirements, offering lowest p…
The Synopsys ARC® EM Family, based on the ARCv2 instruction set architecture (ISA) includes ARC EM4 and EM6, DSP-enhanced EMxD pr…
The latest additions to the Synopsys ARC® ARC HS family, the 32-bit ARC HS5x and 64-bit HS6x processors, are based on the new ARC…
ARC Functional Safety Software
Today’s complex automotive applications require robust safety related hardware and software to meet the increasingly stringent au…
ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Ar…
ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Ar…
ARC EM7D DSP Enhanced 32-bit processor core with caches, ARCv2DSP ISA, for low power embedded DSP ap
The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Ar…
ARC EM5D Enhanced 32-bit processor core, ARCv2DSP ISA, for low power embedded DSP applications
The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Ar…
Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
Memory management unit (MMU) option for ARC HS5x and HS6x processors
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
ARC HS68 64-bit, dual-issue processor with MMU, ARCv3 ISA, for embedded Linux applications
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…