Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers
The L30(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requireme…
RISC-V processor - 32 bit, 5-stage pipeline
The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requ…
The Serial Peripheral Interface or SPI-bus is a simple 4- wire serial communications interface used by many peripheral chips that…
32 Bit - Embedded RISC-V Processor Core
The L31(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requireme…
32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeSt…
32 Bit - Embedded RISC-V Processor Core
Codasip® L110 is a 32-bit RISC-V embedded processor, focused on small-area and low-power applications.
32 bit - Compact RISC-V Processor Core
The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements.
Serial Peripheral Interface - Master/Slave with single, dual, quad and octal SPI Bus support
The DOSPI is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory.
Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
The SPI IP is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory.
Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support
The DQSPI is a revolutionary quad SPI designed to offer the fastest operations available for any serial SPI memory.
Our solution is a hardware implementation of media access control protocol defined by the IEEE standard.
10/100 Mb Media Access Controller with RMII
Our solution is a hardware implementation of media access control protocol defined by the IEEE standard.
10/100 Mb Media Access Controller
Our solution is a hardware implementation of media access control protocol defined by the IEEE standard.
32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
900 Series processors include four different classes: N900 (32 bit), U900 (32 bit + MMU), NX900 (64 bit) and UX900 (64 bit + MMU).
32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
600 Series processors include four different classes: N600 (32 bit), U600 (32 bit + MMU), NX600 (64 bit) and UX600 (64 bit + MMU).
SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
The DB-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (bot…
Cryptographic engine using the DES, Triple-DES or AES
The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES, AES or SM4 algorithms.
The MIPI SLIMbus Host v2.0 typically resides in a mobile platform’s application processor and provides two-wire, multipurpose con…
SPI Controller IP- Master/ Slave, Parameterized FIFO, Avalon Bus
The Digital Blocks DB-SPI-MS-AVLN is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave …
The DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI…