CXL 2.0 Controller IP Listing

The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…

• CXL
• In production
• Available
• CXL, PCI-SIG

The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…

• CXL
• In production
• Available
• CXL, PCI-SIG

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…

• PCIe / CXL IDE

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…

• CXL
• FPGA proven
• Immediate
• CXL V2.0

The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.

• CXL

The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…

• CXL
• Available on request
• Available

Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Controller IP for CXL addresses…

• CXL
• Silicon Proven

The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.

• CXL
• Available
• CXL, PCI-SIG

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Panmnesia Compute Express Link (CXL) IP implements all necessary logic for CXL device, host, and switch.

• CXL

Most PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express®…

• TSMC
• 5nm
• N5
• Silicon Proven

Compliant with CXL Specification 2.0

• CXL