Qualitas Semiconductor
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HQ:
South Korea
The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal …
- UCIe
Compare 68 UCIe PHY IP Listing from 21 vendors
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SkyeChip• HQ: Malaysia
Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for …
- UCIe
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Neuron IP Inc.• HQ: Canada
The UCIe PHY & D2D Adapter IP portfolio includes 32Gbps UCIe- (UCIe-A) & Standard (UCIe-S) cores as per the latest UCIe v1.1 spec…
- UCIe
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Ventana Micro Systems Inc.• HQ: USA
The second-generation high-performance RISC-V CPU delivers a major leap in compute capability, designed for deployment across dat…
- CPU
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Chip Interfaces ApS• HQ: Denmark
Industry , AXI5-Stream Solution for UCIe D2D Stacks The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Strea…
- UCIe
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Synopsys, Inc.• HQ: USA
The SLM Signal Integrity Monitor (SIM) IP enables signal quality measurement for die-to-die interfaces.
- Monitoring
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Siemens Digital Industries Software• HQ: USA
Accelerated confidence in simulation-based verification of RTL designs with Ethernet networking interfaces Avery TSN Ethernet Ver…
- Ethernet
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Chip Interfaces ApS• HQ: Denmark
Industry , Silicon Proven, 32 Gbps per pin, backed by a portfolio of verification tools, PHY interoperability and integration.
- UCIe
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Universal Chiplet Interconnect Express PHY IP - GLOBALFOUNDRIES® 22FDX®
Racyics GmbH• HQ: GermanyThe Racyics UCIe PHY is an energy-efficient chiplet interconnect IP solution for consumer and automotive applications.
- GlobalFoundries
- 22nm
- FDX
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UCIe Controller add-on CXL2 Protocol Layer
Synopsys, Inc.• HQ: USAThe UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
- UCIe
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UCIe Controller add-on CXL3 Protocol Layer
Synopsys, Inc.• HQ: USAThe UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
- UCIe
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UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
Synopsys, Inc.• HQ: USAThe UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
- UCIe
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Cadence Design Systems, Inc.• HQ: USA
Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Univer…
- UCIe
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UCIe-S PHY for Standard Package (x16) in TSMC N6, North/South Orientation
Synopsys, Inc.• HQ: USAThe UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
- TSMC
- 6nm
- N6
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Synopsys, Inc.• HQ: USA
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
- TSMC
- 5nm
- N5A
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UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation
Synopsys, Inc.• HQ: USAThe UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
- UCIe
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UCIe-A PHY for Advanced Package (x64) in TSMC N5, North/South Orientation
Synopsys, Inc.• HQ: USAThe UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
- UCIe
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Synopsys, Inc.• HQ: USA
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
- UCIe
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UCIe-S PHY for Standard Package (x16) in TSMC N4P, North/South Orientation
Synopsys, Inc.• HQ: USAThe UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
- TSMC
- 4nm
- N4P
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UCIe-A PHY for Advanced Package (x64) in TSMC N3E, North/South Orientation
Synopsys, Inc.• HQ: USAThe UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
- TSMC
- 3nm
- N3E