PCI Express 3.0 IP Listing

The 8b-10b Verification IP provides an effective &efficient way to verify the 8b-10b components of an IP or SoC.

• Ethernet

Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is complia…

• PCI Express

Xilinx provides a PCI Express Gen3 integrated block for PCI Express® (PCIe) in the Virtex®-7 XT and HT family of FPGAs.

• PCI Express

The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and…

• Samsung
• 28nm
• FDS
• Silicon Proven

The PCIe Gen 5 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 5 interfa…

• PCI Express

Used by all PCIe, IP, and SoC design verification teams for all generations.The Cadence® Verification IP (VIP) for PCI Express® (…

• PCI Express

The USB3.0 PHY IP is designed according to the USB 3.0, USB2.0 Specification.

• Single-Protocol PHY

The USB3.0 PHY IP is designed according to the USB 3.0, USB2.0 Specification.

• Samsung
• 28nm
• FDS
• Silicon Proven

The PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and …

• Multi-Protocol PHY

The NVMe 2.2 Verification IP provides an effective & efficient way to verify the components interfacing with the PCIe/AXI interfa…

• NVMe Controller

The NVMe 2 Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP…

• NVMe Controller

The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…

• CXL
• Available on request
• Available

PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design.

• PCI Express
• Now

The USB 3.0 Device Upgrade IP enables designers in the PC, mobile, consumer and communication markets to bring significant power …

• USB

The USB 3.0 Device IP core enables designers in the PC, mobile, consumer and communication markets to bring significant power and…

• USB

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL