USB 2.0 OTG IP Listing

The USB 2.0 OTG IP Core is compliant with the OTG Supplement Rev.

• USB

Our company offers a configurable and adaptable USB 2.0 OTG controller IP core, suitable for a wide range of applications.

• USB
• In Production
• Immediate
• USB2.0 specifications Revis…

The Arasan USB 2.0 OTG DRD IP Core is compliant with the OTG Supplement Rev.

• USB

The USB 2.0 OTG ESD Protection library provides a comprehensive ESD solution for USB 2.0 hard macro cells.

• GlobalFoundries
• 65nm
• G
• Silicon Proven

IP

• SMIC
• 55nm
• LL
• Silicon Proven

USB2.0 OTG PHY, UMC 55nm eFlash process.

• UMC
• 55nm

OTG USB2.0 UMC 40 nm LP/RVT process.

• UMC
• 40nm
• LP

USB 2.0 host On-The-Go PHY, UMC 0.25um Logic process.

• UMC
• 250nm

USB 2.0 On-The-Go PHY, UMC 0.18um GII Logic RVT/FSG process.

• UMC
• 180nm
• G

USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process.

• UMC
• 130nm
• HS

USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 55nm LP Low-K Logic process.

• UMC
• 55nm
• LP

USB2.0 OTG PHY, UMC 90nm LL Low-K -RVT process 2.5V OD 3.3V.

• UMC
• 90nm
• LL

USB2.0 OTG PHY, UMC 90nm SP/RVT/ Low-K process.

• UMC
• 90nm
• SP

USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 65nm LP/RVT Low-K Logic process.

• UMC
• 65nm
• LP

USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 65nm low leakage RVT Low-K process.

• UMC
• 65nm
• LL

USB2.0 OTG (VDT and ID are included in PHY), UMC 65nm SP/HVT Low-K process.

• UMC
• 65nm

OTG USB 2.0 PHY (VDT and ID are included in PHY), UMC 55nm SP Low-K Logic process.

• UMC
• 55nm
• SP

USB2.0 OTG PHY, UMC 0.18um eFlash process.

• UMC
• 180nm

USB2.0 OTG PHY, UMC 0.18um E-flash process.

• UMC
• 180nm

USB OTG 2.0 PHY, UMC 0.153um Logic process.

• Single-Protocol PHY