Programmable Low Power SERDES Receiver on TSMC CLN65LP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN28HPL
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen3 SERDES PHY on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen3 SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Low Power Frac-N on TSMC CLN28HPC+
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.
Low Power Frac-N on TSMC CLN28HPC
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.
Low Power Frac-N on TSMC CLN22ULL
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.
Low Power Frac-N on TSMC CLN16FFC
The low power Fractional-N PLL addresses power sensitive designs required for IOT, mobile and other low power applications needin…
Low Power Frac-N on TSMC CLN12FFC
The low power Fractional-N PLL addresses power sensitive designs required for IOT, mobile and other low power applications needin…
Low Power 1-22G PCIe Gen4 / SAS4 PHY on TSMC CLN16FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS) capable…
Custom Programmable Low Power SERDES on GLOBALFOUNDRIES 65G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Automotive Grade Frac-N on TSMC CLN22ULL
The low power Fractional-N PLL addresses power sensitive designs required for IOT, mobile and other low power applications needin…
MSquare's LPDDR4X PHY is a transceiver physical layer IP interface solution designed for ASICs and SOCs.
This audio codec integrates 2-channel 24-bit sigma-delta ADCs and 2-channel 24-bit sigma-delta DACs, and fractional audio PLL to …
The Gen 2 DDR multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard LPDDR2, LPDDR3…
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
USB1.1 FS/LS PHY, GloabalFoudries 55EF
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.