Actt
•
HQ:
China
IP
- PLL
- Silicon proven
- immediate
Compare 3,564 PLL IP Listing from 105 vendors
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Ultra-low power and low jitter PLL
Actt• HQ: ChinaIP
- PLL
- proven
- immediate
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Linear Regulator, Low-noise optimized for sensitive application such as RF or PLL blocks
Dolphin Semiconductor• HQ: France-
- TSMC
- 65nm
- GP
- Pre-Silicon
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Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
Dolphin Semiconductor• HQ: FrancenLR-Charny-ref-[1.62-3.63]-[0.8-2.5]-Ixx.02, as any Power Management Virtual Component designed by Dolphin Design, is readily ret…
- SMIC
- 40nm
- LL
- Pre-Silicon
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PLL (Spread Spectrum) IP, UMC 40nm LP process
Faraday Technology• HQ: TaiwanInput clock:8MHz, output clock range:720 ~ 1680MHz wide-range SSCG, UMC 40nm LP process.
- UMC
- 40nm
- LP
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PLL (Spread Spectrum) IP, UMC 40nm LP process
Faraday Technology• HQ: TaiwanInput clock range:5 ~ 1280MHz, output clock range:15.625 ~ 2000MHz wide-range SSCG, UMC UMC 40nm LP/LVT Low-K Logic process.
- UMC
- 40nm
- LP
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PLL (Spread Spectrum) IP, Input: 5MHz - 1280MHz, Output: 15.625MHz - 2000MHz, UMC 55nm LP process
Faraday Technology• HQ: TaiwanInput 20M-135MHz, output 20M-135MHz SSCG, UMC 0.18um Logic process.
- UMC
- 55nm
- LP
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PLL IP, Input: 25MHz, Output: 156.25MHz, UMC 40nm LP process
Faraday Technology• HQ: TaiwanJitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for Ji…
- UMC
- 40nm
- LP
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Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
Dolphin Semiconductor• HQ: FrancenLR-Charny-ref-[1.62-3.63]-[0.8-2.5]-Ixx.02, as any Power Management Virtual Component designed by Dolphin Design, is readily ret…
- TSMC
- 55nm
- GP
- Pre-Silicon
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1.1V, Max frequency 1.5GHz PLL
SMIC• HQ: China1.1V, Max frequency 1.5GHz
- SMIC
- 40nm
- Silicon Proven
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PLL (Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/FSG process
Faraday Technology• HQ: Taiwan5GHz SSCG with 25MHz reference clock, UMC 0.11um 20T HS/FSG Logic process.
- UMC
- 110nm
- HS
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PLL (Spread Spectrum) IP, 20MHz - 70MHz, UMC 0.18um G2 process
Faraday Technology• HQ: TaiwanUMC 0.18um GII Logic process 20MHz-70MHz delay-type spread-spectrum clock generator.
- UMC
- 180nm
- G
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Faraday Technology• HQ: Taiwan
Input clock range:10M ~ 1280MHz, output clock range:15.625M ~ 2000MHz wide-range SSCG, UMC 0.11um HS/AE (AL Enhancement) 2T Logic…
- UMC
- 110nm
- HS
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PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
Faraday Technology• HQ: Taiwan5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
- UMC
- 110nm
- HS
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PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
Faraday Technology• HQ: Taiwan5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
- UMC
- 110nm
- HS
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PLL CMOS phase-frequency detector with CMOS charge pump
NTLab• HQ: LithuaniaPhase-frequency detector (PFD) forms control signal for VCO tuning.
- PLL
- Pre-silicon verification
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PLL 24.84 MHz phase-frequency detector with charge pump
NTLab• HQ: LithuaniaPhase-frequency detector (PFD) forms control signal for VCO tuning.
- PLL
- Silicon proven
- Now
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PLL ECL phase-frequency detector with ECL charge pump
NTLab• HQ: LithuaniaPhase-frequency detector (PFD) forms control signal for VCO tuning.
- PLL
- Pre-silicon verification
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PLL ECL phase-frequency detector with ECL charge pump
NTLab• HQ: LithuaniaPhase-frequency detector (PFD) forms control signal for VCO tuning.
- PLL
- Pre-silicon verification
- Now
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PLL CMOS phase-frequency detector with ECL charge pump
NTLab• HQ: LithuaniaPhase-frequency detector (PFD) forms control signal for VCO tuning.
- PLL
- Pre-silicon verification
- Now