PLL IP, Input: 372M - 540MHz, Output: 5MHz - 400MHz, UMC 0.13um HS/FSG process
Faraday Technology
•
HQ:
Taiwan
Input 372M ~ 540MHz, output 5M ~ 400MHz, PLL, UMC 0.13um HS/FSG Logic process.
- UMC
- 130nm
- HS
Compare 3,564 PLL IP Listing from 105 vendors
-
-
Faraday Technology• HQ: Taiwan
Input 5M-200MHz, output 12.5M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.11um CMOS Image Sensor process.
- UMC
- 110nm
-
Faraday Technology• HQ: Taiwan
Input 5M-200MHz, output 12.5M-300MHz, frequency synthesizable PLL, UMC 0.11um CMOS Image Sensor process.
- UMC
- 110nm
-
PLL IP, Input: 32.768KHz, Output: 12MHz - 48MHz, UMC 0.11um HS/FSG process
Faraday Technology• HQ: TaiwanInput 32.768KHz, output 12M-48MHz, PLL, UMC 0.11um HS/Copper Logic process.
- UMC
- 110nm
- HS
-
VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USA
Designed for audio clock generation, this PLL integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control …
- SMIC
- 180nm
- G
-
VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USA
This PLL is designed for audio clock generation.
- SMIC
- 130nm
- G
-
Fractional N PLL 8.5-11.3GHz in GF N65
Pacific MicroCHIP Corp.• HQ: USAPMCC_PLL12GFN is a macro-block designed for synthesizing the frequencies required for fiber optic transceivers and serdes using c…
- GlobalFoundries
- 65nm
- LP
- In Production
-
VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USA
This PLL is designed for audio clock generation.
- PLL
-
SMIC 0.13um 1.2v / 3.3v Audio PLL
VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USAThis PLL is designed for audio clock generation.
- SMIC
- 130nm
- G
-
VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USA
This PLL is designed for audio clock generation.
- SMIC
- 130nm
- G
-
VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USA
This PLL is designed for audio clock generation.
- IBM
- 65nm
- LPe
-
PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270)
V-Trans Microelectronics• HQ: CHINAThe VT18PLL500 is a macro cell for clock generation.
- PLL
- silicon proven
- now
-
Faraday Technology• HQ: Taiwan
Input 25M-500MHz, output 1000M-1500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT process.
- UMC
- 65nm
-
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 65nm SP process
Faraday Technology• HQ: TaiwanInput 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT Logic process.
- UMC
- 65nm
-
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 65nm SP process
Faraday Technology• HQ: TaiwanInput 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 65nm SP/RVT Logic process.
- UMC
- 65nm
-
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 300MHz - 600MHz, UMC 65nm LL process
Faraday Technology• HQ: TaiwanInput 20M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 65nm LL Logic/RVT Low-K process.
- UMC
- 65nm
- LL
-
PLL (Frequency Synthesizer) IP, Input: 5MHz - 500MHz, Output: 31.25MHz - 500MHz, UMC 65nm SP process
Faraday Technology• HQ: TaiwanInput 5M-500MHz, output 31.25M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT process.
- UMC
- 65nm
-
SMIC 0.13um 1.2v/3.3v PLL Specification
VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USAThis PLL is designed for audio clock generation.
- SMIC
- 130nm
- G
-
VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USA
This PLL is designed for audio clock generation.
- SMIC
- 130nm
- G
-
40-450MHz Programmable Clock Generator PLL, SMIC0.13um
Archband Labs Inc.• HQ: USAThe AR530S13 is a low power programmable phase locked loop (PLL) featured with wide output frequency range from 50MHz to 450MHz.
- SMIC
- 130nm
- G
- In Production