PLL (Frequency Synthesizer) IP, Input: 25MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 28nm HPM process
Input 25M-50MHz, output 1000M-2000MHz, frequency synthesizable PLL, UMC 28nm Logic and Mixed-Mode HPM process.
- UMC
- 28nm
- HPM
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 28nm HPM process
Input 25M-50MHz, output 1000M-2000MHz, frequency synthesizable PLL, UMC 28nm Logic and Mixed-Mode HPM process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 200MHz, Output: 1GHz -1.5GHz, UMC 90nm SP process
Input 25M-200MHz, output 1000M-1500MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 28nm HPM process
Input 20M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 28nm Logic and Mixed-Mode HPM process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 28nm HLP process
Input 20M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 28nm Logic and Mixed-Mode HLP process.
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.11um HS/AE (AL Enhancement) Logic process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 20M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output frequency synthesizable PLL, UMC…
Half low pass filter area compare with FXPLL362HJ0G, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400M…
PLL (Frequency Synthesizer) IP, Input: 1MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 1M-300MHz, output 20M-300MHz, frequency synthesizable PLL, 0.18um GII Logic process.
PLL (Frequency Synthesizer) IP, Input: 1MHz - 200MHz, Output: 25MHz - 380MHz, UMC 0.18um G2 process
Input 1M-200MHz, output 25M-380MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
PLL (Frequency Synthesizer) IP, Input: 12MHz, Output: 120MHz / 540MHz, UMC 40nm LP process
Input 12MHz, output clock1 540MHz and output clock2 120MHz, PLL, UMC 40nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 90nm SP process
Input 12M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 90nm SP Logic process.
PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 40nm LP process
miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 250MHz and 500MHz, UMC 40nm LP/RVT Logic proces…
Input 12M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm SP process
Input 10M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
PLL IP, Input: 25MHz, Output: 156.25MHz, UMC 40nm LP process
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for Ji…