Power on Reset IP, Input: 1.2V, Vrr=Vfr=0.8V, UMC 55nm LP process
Vrr=Vfr=0.8V, input VCC=1.2V, 1.2V Power On Reset, UMC 55nm 2T LP/RVT Low-K Logic process.
- UMC
- 55nm
- LP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Power on Reset IP, Input: 1.2V, Vrr=Vfr=0.8V, UMC 55nm LP process
Vrr=Vfr=0.8V, input VCC=1.2V, 1.2V Power On Reset, UMC 55nm 2T LP/RVT Low-K Logic process.
Power on Reset IP, Input: 1.2V, UMC 0.13um LL/FSG process
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=10.7uA, Core type, Power On Reset, UMC 0.13um LL Logic(FSG) process.
Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA, HS process with B-type IO., Power On Reset, UMC 0.13um HS/FSG Logic process.
Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA, HS process with A-type IO., Power On Reset, UMC 0.13um HS/FSG Logic process.
Power on Reset IP, Input: 1.1V, UMC 40nm LP process
Vrr=0.8V, Vfr=0.65V, input VCC=1.1V, 1.1V Power On Reset, UMC 40nm LP/RVT Low-K Logic process.
Power on Reset IP, Input: 1.0V, UMC 90nm SP process
Vrr=0.67V Vfr=0.63V, input 1.0V, Core type, Power On Reset (with Self-Test Circuit), UMC 90nm SP/RVT Logic Low-K process.
PLL (Spread Spectrum) IP, UMC 40nm LP process
Input clock:8MHz, output clock range:720 ~ 1680MHz wide-range SSCG, UMC 40nm LP process.
PLL (Spread Spectrum) IP, UMC 40nm LP process
Input clock range:5 ~ 1280MHz, output clock range:15.625 ~ 2000MHz wide-range SSCG, UMC UMC 40nm LP/LVT Low-K Logic process.
PLL (Spread Spectrum) IP, Input: 5MHz - 1280MHz, Output: 15.625MHz - 2000MHz, UMC 55nm LP process
Input 20M-135MHz, output 20M-135MHz SSCG, UMC 0.18um Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm SP process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, 0.18um GII Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.18um GII Logic process.
Input 5M-200MHz, output 25M-400MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.
Input 5M-200MHz, output 12.5M-200MHz, frequency synthesizable PLL, UMC 0.13um LL Logic/FSG process.
Input 5M-100MHz, output 62.5M-1000MHz, frequency synthesizable PLL with power/ground pad, UMC 0.13um HS/FSG Logic process.
Input 5M-100MHz, output 62.5M-1000MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, , Output: 20MHz - 300MHz, UMC 0.25um process
Input 5M-100MHz, output 20M-300MHz, frequency synthesizable PLL, 0.25um Logic process.
PLL (Frequency Synthesizer) IP, Input: 4MHz - 200MHz, Output: 20MHz - 400MHz, UMC 0.18um G2 process
Input 4M-200MHz, output 20M-400MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
Input 45k-60KHz, output 81M- 132MHz, PLL, UMC 0.11um HS/FSG Logic process.
UMC 0.13um HS/FSG process PLL for DDR2.