USB2.0 Dual-Role PHY, Samsung LF6S
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
- USB 2.0
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
USB2.0 Dual-Role PHY, Samsung LF6S
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, Samsung LF6
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
RISC-V Vector Extension
RISC-V Real-time Processor
RISC-V High Performance Processor
RISC-V High Performance Processor
Gen7 supports 128Gbps and backward compatible with previous versions of PCIE.
An interconnect component connects initiators and targets in a system.
The bus converter module transforms 64-bit wide initiator data buses to smaller 32-bit target data buses or vice-versa.
Various bus types of protocols are available and employed in many applications, all of which require a bridge to operate safely a…
Decoder logic controls numerous targets based on input from the initiator.
The pervasive nature of Ethernet has made it an integral part of our connected world, driving communication speeds up to 1.6T.
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process
RISC-V IP - Dual Issue Power Efficient Application
Dual Issue Power Efficient Application Core - VisionL is a dual-issue power-efficient application core designed for applications …
RISC-V IP - Dual Issue Embedded Application
Dual Issue Embedded Application Core - VisionG is a dual-issue embedded application core, providing high-performance computing ca…
RISC-V IP - Entry Level Application Core
Entry Level Application Core - VisionC is an entry-level application core that strikes the perfect balance between cost-effective…
RISC-V IP - Microcontroller Unit (MCU) level
MCU Level Core - VisionA is our Microcontroller Unit (MCU) level core, offering exceptional versatility and efficiency for embedd…
TRNG (True Random Number Generator) NIST SP800-90C
TRNG Core meets NIST SP 800-90A/B standard It is the basis of the Root of Trust System, mainly it comes with other Security Eleme…
Silicon Proven Hardware Root of Trust
The Root of Trust (RoT) is always the trusted root within a cryptographic system.
Ultra-low power RISC-V microcontroller CPU
IP
Streamline Ventana technology integration into high-performance systems, fully leveraging third-party IP, while applying RISC-V s…