SMIC 0.13μm 1.62~3.3v->1.2v Power Regulator
Targeted in SMIC 0.13μm 1.2v/3.3v logic process, current design of Power Regulator is to provide 1.2v power supply which is regul…
- SMIC
- 130nm
- G
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
SMIC 0.13μm 1.62~3.3v->1.2v Power Regulator
Targeted in SMIC 0.13μm 1.2v/3.3v logic process, current design of Power Regulator is to provide 1.2v power supply which is regul…
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for generating system clock.
This PLL is designed for audio clock generation.
SMIC 0.13um 1Channel 10Bit 10MHz DAC
S13V33_R2RDAC_01 is a 10bit@10MHz DAC IP which implements a 7-bit (from D [0] to D [6]) R2R_Ladder and 3-bit thermometer decoder …
IBM 65nm 24-bit Stereo Sigma-Delta ADC
The I65GV25_ADC_01 specifies the design of a high-performance 24-bit stereo Audio ADC for portable digital audio systems.
IBM 65nm 24bit Sigma-Delta DAC
The I65GV25_DAC_01 specifies the design of a high-performance 24-bit stereo Audio DAC for portable digital audio systems.
This PLL is designed for audio clock generation.
This analog 2-1 MUX is designed for low speed application.
IBM 65nm 3.3v-1.0v Power Regulator
This IP is a 3.3V to 1.0V power regulator in IBM 65nm 1.0V/2.5V process.
IBM 65nm 1.0/2.5V 32768Hz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.
IBM 65nm 12-bit 1M/200K Single/Differential 2.5v Rail to Rail SAR ADC
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
This IP is a programmable Analog PLL suitable for high speed clock generation.
IBM10SF 1.0v/2.5v APLL Brief Specification
This IP is a programmable Analog PLL suitable for high speed clock generation.
The AHB External Bus Interface (EBI) allows a CPU or AHB Master component (such as a DMA core) to transmit and receive data to an…
The Controller Area Network is a high reliable serial bus protocol defined in the Bosch CAN specification 2.0B.
HDMI 1.4 transmitter IP core is ideal for DVD, Blu-Ray Disc players, set-top boxes, A/V receivers
Analogix offers its silicon-proven HDMI IP cores (digital plus analogix PHY) for integration into customer's system-on-chip produ…
Ethernet AVB Endpoint IP LogiCORE
Ethernet AVB has been merged with the AXI TEMAC IP and AXI Ethernet IP.
The ChipScope PLB IBA core is a specialized Bus Analyzer core designed to debug embedded systems that contain the IBM CoreConnect…
The ChipScope OPB IBA core is a specialized Bus Analyzer core designed to debug embedded systems containing the IBM CoreConnect O…