Multi-Port Memory Controller (DDR/DDR2/SDRAM)
MPMC is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2 memory.
- Controller
- DDR2
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Multi-Port Memory Controller (DDR/DDR2/SDRAM)
MPMC is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2 memory.
Mixed-Mode Clock Manager (MMCM) Module
The MMCM primitive in Virtex®-6 parts is used to generate multiple clocks with defined phase and frequency relationships to a giv…
The PLBV46 Master Burst is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE™ products.
The On-Chip Peripheral Bus (OPB) to Processor Local Bus (PLB v4.6) Bridge module translates OPB transactions into PLBV46 transact…
Differential Signaling IO Buffer
The Utility Differential Signaling Buffer core generates corresponding buffer to bring off-chip differential signals into interna…
The Clock Generator module provides clocks according to clock requirements.
ChipScope PRO Virtual Input/Output (VIO)
The LogiCORE™ IP ChipScope™ Pro Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal F…
Chipscope PLBv46 Integrated Bus Analyzer (IBA)
The ChipScope™ PLB IBA core is a specialized Bus Analyzer core designed to debug embedded systems that contain the IBM CoreConnec…
ChipScope Integrated Logic Analyzer (ILA)
The LogiCORE™ IP ChipScope™ Integrated Logic Analyzer (ILA) core is a customizable logic analyzer core that can be used to monito…
ChipScope Integrated Controller (ICON)
The LogiCORE® IP ChipScope Pro Integrated core (ICON) provides an interface between the JTAG Boundary Scan (BSCAN) interface of t…
The Multiply Adder IP performs a multiplication of two operands and adds (or subtracts) the full-precision product to a third ope…
Virtex-6 Embedded Tri-mode Ethernet MAC Wrapper
Xilinx provides a Virtex-6 Integrated Tri-mode Ethernet MAC core with integrated serial interface to ensure first time success in…
Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA.
Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA Aurora is a LogiCORE™ IP designed to enab…
Virtex-6 Integrated Block for PCI Express (PCIe)
Xilinx provides a Virtex-6 FPGA Endpoint solutions for PCI Express® (PCIe) to configure the Virtex-6 FPGA Integrated Block for PC…
Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe)
Xilinx provides a Spartan-6 FPGA Integrated Endpoint solution for PCI Express® (PCIe) to configure the Spartan-6 FPGA Integrated …
The Video Timing Controller LogiCORE IP is a general purpose video timing detector and generator.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Color Filter Array Interpolation
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.