IBERT for 7 Series GTH Transceivers
The customizable LogiCORE™ IP Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTH transceivers is designed for eva…
- Test / Debug
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
IBERT for 7 Series GTH Transceivers
The customizable LogiCORE™ IP Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTH transceivers is designed for eva…
The LogiCORE™ I/O Module is a integrated and light-weight implementation of a standard set of peripherals.
Xilinx provides a GMII to RGMII LogiCORE for connecting to the Zynq-7000 integrated Ethernet MAC The Xilinx LogiCORE™ IP Gigabit …
ChipScope Pro IBERT for 7 Series GTX
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Kintex®-7 FPGA GTX transceivers is a customizable core that…
ChipScope Pro IBERT for 7 Series GTH
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Kintex™-7 FPGA GTX transceivers is a customizable core that…
Included at no additional charge with ISE software.
The AXI4-Stream Protocol Checker core monitors AXI4-Stream interfaces for protocol violations and provides an indication of which…
Included at no additional charge with Vivado and ISE Design Suite.
The AXI Virtual controller is provided under the terms of the XILINX End User License and is included with ISE® and Vivado™ desig…
The LogiCORE™ System Cache provides system level caching capability for AXI-4 based systems.
The AXI Protocol Checker core is designed to monitor AXI interfaces.
Included at no additional charge with ISE Embedded, Vivado Design and System Edition software AXI Performance Monitor has the cap…
Included at no additional charge with EDK software.
The LogiCORE™ IP Controller Area Network (CAN) product specification defines the architecture and features of the Xilinx CAN cont…
EdgeQAM IP Core Set (1 x RF Port, 160-Ch, ADI)
Developed in collaboration with Xilinx®, Inc., the RADX™ EdgeQAM IP Core Set is a modular, scalable set of Intellectual Property …
Image scaling is a challenging task, especially when increasing resolution.
Mature solution featuring xHCI Host, Device, and Dual-Role
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V)
TSMC 180 G, SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into ac…
TSMC 180 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery co…
Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
Metal programmable ROM compiler - TSMC 90 nm LP - Non volatile memory optimized for low power - compiler range up to 1024 k