This core extends the Algotronix G3 Encryption Standard (AES) core by providing a secure, standardized method for loading cryptog…
- AES
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
This core extends the Algotronix G3 Encryption Standard (AES) core by providing a secure, standardized method for loading cryptog…
This UHS2PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed i…
This UHS2PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed i…
GNSS Software Receiver (GPS, Galileo, GLONASS, Beidou3, QZSS, SBAS) IP
The Software Receiver is the next generation Global Navigation Satellite System (GNSS) receiver covering GPS and SBAS satellite s…
GSM GPRS EDGE Protocol Stack SW IP
A 2.5G GSM/GPRS/EDGE SW Protocol Stack that has been integrated with multiple basebands and shiped in 1bn phones and M2M modules …
Xilinx 40G/100G Ethernet LogiCORE based on Sarance Technologies Best-In-Class Intellectual Property Xilinx High-Speed Ethernet Lo…
TSMC 130 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery co…
The PowerVR Series6XE range is based on the Rogue architecture and includes single and half-cluster GPUs.
TSMC 55 LPeF, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery …
Foundry sponsored - Two Port Register File compiler - TSMC 55 nm HV - Memory optimized fore high density and high speed - compile…
High Speed Low Power JPEG Codec
IP
The AAC-LC Stereo Audio Encoder (CWda84) is an audio IP core for encoding one stereo stream in real-time.
Legacy-Configurable 8051-Compatible Microcontroller IP
The L8051XC1 core implements an MCS®51-compatible microcontroller that is specially designed to match the timing and peripherals …
sROMet compiler - Memory optimized for high density and high speed - compiler range up to 2M
Foundry sponsored - sROMet compiler - TSMC 55 nm HV - Non volatile memory optimized for high density and high speed - compiler ra…
MPEG-1/2 - Layer I/II Audio Encoder
The MPEG-1/2 – Layer I/II Audio Encoder (CWda74) is an audio IP core for encoding one audio stream in real-time(1).
SATA 3 Host Controller on ARRIA V FPGA
The LDS SATA 3 HOST AR5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA …
HDLC & SDLC Protocol Controller
The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC…
Foundry Sponsored - Single Port SRAM compiler - TSMC 130 nm BCD - Memory optimized for ultra high density and high speed - compil…
Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory otimized for high density and low power - compiler range u…
Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for high density and low power - compiler range …