Geon Secure Execution Processor delivers secure code execution by supporting two secure contexts.
- Security Coprocessor
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Geon Secure Execution Processor delivers secure code execution by supporting two secure contexts.
H.264 High 10 Intra Profile Encoder
The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard.
SATA Host on Xilinx Zynq Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 F…
40G-1K Sess. TCP + UDP Offload Engine
INT 40011 is the only SOC IP Core that implements a full 40G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance…
25G-1K Sess. TCP + UDP Offload Engine
INT 25011 is the only SOC IP Core that implements a full 25G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance…
10 G bit TCP Offload Engine + PCIe/DMA SOC IP
INT 20012 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low Latency and Very High Perfor…
10G-16K Sess. TCP + UDP Offload engine (INT-20011-16K)
INT 20011 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance…
10G TCP Offload Engine+MAC+Host_IF Ultra-Low Latency (SXTOE)
INT 20011 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance…
10G UDP Offload Engine UOE+MAC+PCIe+Host_IF Ultra-Low Latency (SXUOE+PCIe)
INT 15012 is the only SOC IP Core that implements a full 10G bit UDP Stack in Handcrafted, Ultra-High Performance, , Flexible and…
10G UDP Offload Engine UOE+MAC+Host_IF Ultra-Low Latency (SXUOE)
INT 15011 is the only SOC IP Core that implements a full 10G bit UDP Stack in Handcrafted, Ultra-High Performance, , Flexible and…
1-Gbit Network Search Engine Controller
customizable hardware IP block.
GF 65nm 1.0V<->3.3V level shifter
GF65nm 1.0V3.3V Level Shfiter Library
GF 65nm 3.3V Standard Cell Library
GF 65nm 3.3V Standard Cell Library
Foundry sponsored - Single Port SRAM compiler - TSMC 55 uLPeFlash - Memory optimized for high density and low power - Dual Voltag…
E31 Balanced performance and efficiency RISC V core
The SiFive E31 Standard Core is the world's most deployed RISC-V core.
UMC 0.18um 9track Standard Cell Library, 1.8v operating voltage
UMC 0.18um Standard Cell Library
TSMC 0.13um 9track Standard Cell Library, 1.2v operating voltage
TSMC 0.13um 9 track Standard Cell Library
IBM 65nm LPE 1.2V<->3.3V Level Shifter
IBM 65nm LPE 1.2V3.3V Level Shifter Library
IBM 65nm LPE 3.3V Standard Cell
IBM 65nm LPE 3.3V Standard Cell Library
SATA 3 HOST IP on ARRIA 10 FPGA
The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL AR…