2.5V General Purpose Staggered IO Pad Set
A full range of power pads is provided to enable the system designer different options for separate core power (VDD and VSS) and …
- GlobalFoundries
- 40nm
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
2.5V General Purpose Staggered IO Pad Set
A full range of power pads is provided to enable the system designer different options for separate core power (VDD and VSS) and …
Gigabit Ethernet PHY (in production)
GNSS Ultra low power (GPS, Galileo, GLONASS, Beidou3, QZSS, IRNSS, SBAS) Digital IP
This Ultra Low Power GNSS Multi-Constellation Digital IP is extracted from a production chipset supporting all the major constell…
Industry- Performance and Efficiency for Inference at the Edge Based on a new, class- architecture, the Arm ML processor’s optimi…
Uncompromised Graphics Performance Play games for longer First-generation Valhall-based graphics processing unit (GPU) for the pr…
Primeexpress PCIE Gen5 digital controller from Primesoc, is well architect,high performance, modular designed and tailor made to …
The Arm Mali-D77 is the second-generation premium display processor based on the Komeda display architecture.
DesignWare Library contains the essential infrastructure IP for design and verification
The DesignWare Library contains the essential infrastructure IP for design and verification including datapath components, AMBA O…
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V1.0/V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v1.0 and D-PHY v1.2”, which consists of Bi-directional 1-Clock a…
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Slave V1.0/V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v1.0 and D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
Floating Point (FP) arithmetic has become more widespread in wireless communications, military applications, aeronautical applica…
Multi Protocol Synchronous Serial Engine IP
The developed IP integrates basic serial interface protocols like UART, SPI and I2C into a single AXI interface port.
FSK Demodulator,BCH Decoder,Command Decoder,Validator,Convolution Encoder IPs
A lot of development for implementing communication subsystem for a student nano-satellite was also undertaken.
Analog Data Acquisition Controller IP
The analog data acquisition controller IP interfaces various industry standard ADCs with digital interfaces like SPI, I2C, parall…
The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface.
3.3V Power Support I/O Pad Set
The 3.3V Support: Power library provides a full complement of cells to support the assembly of a pad ring by abutment.
3.3V 100 MHz Oscillator I/O Pad Set
The 1.8V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …
1.8V Programmable 100MHz Oscillator I/O Pad Set
The Oscillators library provides a programmable oscillator for on-chip asynchronous clock generation with an appropriate external…
1.8V Power Support I/O Pad Set
The 1.8V Support: Power library provides a full complement of cells to support the assembly of a pad ring by abutment.
Neural network processor designed for edge devices
Kneron NPU IP Series are neural network processors that have been designed for edge devices.