Learn more about Standard Cell Libraries IP core
This article describes five areas where designers can take advantage of this new process with the latest logic library technology to optimize the performance, power and area of their system on chips (SoCs).
Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and complexity of DRC rules is increasing and designs are getting bigger. The need for a better understanding of the manufacturing issues during the design phase raises concerns about how to best address these issues.
This paper, aimed at decision makers within product development companies with responsibility for specifying device connectivity, provides an up-to-date report on the status of Certified Wireless USB technology. It explores the favorable economic factors