Learn more about Standard Cell Libraries IP core
This article describes five areas where designers can take advantage of this new process with the latest logic library technology to optimize the performance, power and area of their system on chips (SoCs).
Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and complexity of DRC rules is increasing and designs are getting bigger. The need for a better understanding of the manufacturing issues during the design phase raises concerns about how to best address these issues.
This paper, aimed at decision makers within product development companies with responsibility for specifying device connectivity, provides an up-to-date report on the status of Certified Wireless USB technology. It explores the favorable economic factors
Standard cells libraries are usually designed to operate at a specific value of supply voltage referred to as “nominal voltage”. This article details the performance trade-offs in terms of power consumption and speed when decreasing power supply voltage, as well as a methodology to determine the lowest value to use.
If someone had predicted fifteen years ago that 28nm would still be the foundation for many new chip designs, the idea might have seemed unlikely. Process technology was advancing rapidly, and the industry’s attention was firmly fixed on shrinking geometries. Each new node promised more transistors, greater integration, and higher performance.
Adaptability is essential for digital twin systems due to constantly evolving environments – Learn how eFPGA hardware enables robust and adaptable systems
