Vendor: Aragio Solutions Category: GPIO

1.8V Power Support I/O Pad Set

The 1.8V Support: Power library provides a full complement of cells to support the assembly of a pad ring by abutment.

TSMC 7nm N7+ Silicon Proven View all specifications

Overview

The 1.8V Support: Power library provides a full complement of cells to support the assembly of a complete pad ring by abutment. It is supplied as a standard addition to the GPIO libraries and other I/O library offerings from Aragio Solutions that use a compatible pad ring bus structure.

These 7nm libraries are available in inline and staggered flip chip implementations.

The included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous
VDD/VSS for robust ESD protection.

Key features

  • ESD Protection:
    • JEDEC compliant
      • 2KV ESD Human Body Model (HBM)
      • 500 V ESD Charge Device Model (CDM)
    • Latch-up Immunity:
      • JEDEC compliant
        • Tested to I-Test criteria of ± 100mA @ 125°C

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7+ Silicon Proven

Specifications

Identity

Part Number
RGO_TSMC07_18V18_7FF_20C_SPT
Vendor
Aragio Solutions
Type
Silicon IP

Provider

Frequently asked questions about GPIO Pad Library IP cores

What is 1.8V Power Support I/O Pad Set?

1.8V Power Support I/O Pad Set is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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