Vendor:
Faststream Technologies
Category:
SPI / QSPI XSPI
Multi Protocol Synchronous Serial Engine IP
The developed IP integrates basic serial interface protocols like UART, SPI and I2C into a single AXI interface port.
Overview
The developed IP integrates basic serial interface protocols like UART, SPI and I2C into a single AXI interface port. The individual modules for these protocols have been implemented in a ruggedized form to avoid bus errors due to interfering noise from various sources thus making it suitable for application in automobile electronics.
Key features
- AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
- Ruggedized SPI, I2C and UART interface
- User configurable number and type of interfaces through a configuration tool
- User configurable parameters of each interface like baudrate/ datarate, modes, length of transmission etc.
- Supports master and slave modes for SPI and I2C interfaces
- Configurable number of slaves on SPI interface
- Contains hardware FIFO for UART, SPI and I2C interfaces with configurable depth upto 1024 words
Block Diagram
FST-MPS-SE IP block diagram
Specifications
Identity
Part Number
FST-MPS-SE IP
Vendor
Faststream Technologies
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about SPI / QSPI XSPI IP core
Unleashing the Power of Communication: Exploring the XSPI Protocol and Arasan Chip Systems' XSPI IP Portfolio
Frequently asked questions about SPI / QSPI / xSPI IP cores
What is Multi Protocol Synchronous Serial Engine IP?
Multi Protocol Synchronous Serial Engine IP is a SPI / QSPI XSPI IP core from Faststream Technologies listed on Semi IP Hub.
How should engineers evaluate this SPI / QSPI XSPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.