Semiconductor IP Cores

Includes both PHY and Memory Controller components, supporting HBM3 SDRAM speeds ranging from 4.8Gbps/pin to 6.4Gbps/pin.

• Controller + PHY

SEC 5nm LVH 6 track High Density Multi-Bits Latch

• Samsung
• 5nm
• SF5
• Silicon Proven

TSMC 12nm FFC 6 track High Density Delay Cells

• TSMC
• 12nm
• FFC
• Silicon Proven

SMIC 0.13um 1.2V3.3V Level Shfiter Library

• SMIC
• 130nm
• G
• Silicon Proven

SMIC 0.13um Power Management Kit Library

• SMIC
• 130nm
• G
• Silicon Proven

SMIC 0.13um 6T HVT High-Density Standard Cell Library

• SMIC
• 130nm
• G
• Silicon Proven

VeriSyno offers network IP solutions tailored for the high-end server market.

• Standard Cell Libraries
• Silicon Proven
• Immediate

This IP is composed of a single to sextuple channel 10-bit, 300MHz DAC designed for 40nm CMOS technology supplied at 3.3V.

• DAC
• Silicon Proven
• Immediate

The HDMI Tx PHY is the physical layer of a single-link HDMI transmitter interface.

• Single-Protocol PHY
• Silicon Proven
• Immediate

The HDMI Rx PHY is the physical layer of an HDMI receiver.

• Single-Protocol PHY
• Silicon Proven
• Immediate

The DDR4 multiPHY is a mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a S…

• Controller + PHY + 1
• DDR4

The DDR multiPHYs are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 S…

• Controller + PHY + 1

The DDR3/2 PHY is a mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design ta…

• Controller + PHY + 1
• DDR3

The XAUI PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into XAUI …

• Single-Protocol PHY
• Silicon Proven
• Immediate

The SATA 6G PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SA…

• Single-Protocol PHY
• Silicon Proven
• Immediate

The PCIe2 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI …

• Single-Protocol PHY
• Silicon Proven; Design Ready(SMIC,28)
• Immediate

The PCIe1 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into comp…

• Single-Protocol PHY
• Silicon Proven
• Immediate

The MIPI D-PHY RX 2/4 Lanes macro implements the physical layer of universal lanes for the MIPI D-PHY interface, stacked in a two…

• MIPI D-PHY

The MIPI D-PHY Bidirectional 2-Lane(4-Lane) macro implements the physical layer of bidirectional universal lanes for the MIPI D-P…

• MIPI D-PHY

The USB 3.0 PHY is a , mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into …

• USB 3.0