The MIPI D-PHY Bidirectional 2-Lane(4-Lane) macro implements the physical layer of bidirectional universal lanes for the MIPI D-P…
- MIPI D-PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The MIPI D-PHY Bidirectional 2-Lane(4-Lane) macro implements the physical layer of bidirectional universal lanes for the MIPI D-P…
The USB 3.0 PHY is a , mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into …
The USB 2.0 PHY is a mixed-signal IP solution designed to implement OTG connectivity in a System-on-Chip (SoC) design targeted to…
>96 dB over 10 Hz bandwidth,
10b ENOB,
92 dBA dynamic range,
The Intra-panel TX PHY IP is a low-power transmitter designed for COG (Chip-on-Glass) and COF (Chip-on-Film) display modules.
SpaceFibre and WizardLink Interface
The GRHSSL IP Core is a versatile and configurable high-speed serial link controller written in VHDL, capable of implementing a S…
USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
MSquare's USB 3.2 PHY IP is designed based on the USB 3.2 Gen2x1 and USB 2.0 specifications from the USB Implementers Forum and d…
High performance image signal processing for auto and industrial markets
PCIE Gen6 digital controller (Dual Mode)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.
PCIE Gen6 digital controller (Root Complex)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
PCIE Gen6 digital controller (End Point)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.
IP
NVMe over TCP IP core - End-to-End NVMe-oF TCP connectivity with no CPU!
NVMeTCP IP is the standalone host side NVMe Over Fabric (NVMe/TCP) controller with no CPU and external memory required.
ES256-XTS IP Core (AES256XTSIP) implement the encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing …
SMPTE 2110-22 Sub-system (TX/RX) IP-cores for JPEG XS video over RTP encapsulation
The intoPIX SMPTE 2110-22 Sub-system IP-cores (TX & RX) are combining the IPX-RTP-XS cores for JPEG XS RTP packetization / depack…
Video Design Framework for Multi-camera Vision Applications
The logiREF-ACAP-VDF "ACAP IP Framework for Multi-Camera Vision Applications" enables Xylon logiVID-ACAP-6CAM ACAP Vision Develop…
The DisplayPort Multi Stream Transport (MST) Topology Management Software implements MST topology management for multiple monitor…