General IO at TSMC 12FFC Process
GPIO is a general-purpose input/output unit that provides basic input/output functionalities.
- TSMC
- 12nm
- FFC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
General IO at TSMC 12FFC Process
GPIO is a general-purpose input/output unit that provides basic input/output functionalities.
General IO at GF 28SLP-HV Process
GPIO is a general-purpose input/output unit that provides basic input/output functionalities.
General IO at GF 130BCDLite2 Process
GPIO is a general-purpose input/output unit that provides basic input/output functionalities.
M31 eMMC/SDIO at HLMC 28HKC+ Process
SD (Secureity Digital) and eMMC (embedded MultiMedia Card) I/Os are non-volatile memory interface technologiesy with high bandwid…
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model.
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model.
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model.
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model.
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model.
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model.
UFSHCI 3.0 - UFS Host Controller Interface
The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platfor…
UFSHCI 4.0 - UFS Host Controller Interface
The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platfor…
ONFI PHY 4.8GT/s for ONFI v6 & JESD230G
The ONFI multi-PHY is a versatile solution that accommodates ONFI4.0 to ONFI6.0 NAND flash interfaces, offering impressive speeds…
NANDPHY 4.8GT/s for ONFI v6 & JESD230G
ONFI I/O is a non-volatile memory interface technology with high bandwidth capabilities, mainly developed for flash storage appli…
ONFI IO v5.1, 3.6GT/s, TSMC N5, 1.2V, N/S orientation, H&V cell
ONFI I/O is a non-volatile memory interface technology with high bandwidth capabilities, mainly developed for flash storage appli…
LPDDR 4/4X PHY, TSMC 12E, N/S orientation
The LPDDR4X multi-PHY supports both LPDDR4 and LPDDR4X memory interfaces at speed up to 4267Mbps, making it an ideal solution for…
MIPI DPHY_TX v1.2, 1C4D, HLMC 40LP
The D-PHY is a popular MIPI physical layer developed for mobile applications because it is a flexible, high-speed, low-power and …
MIPI TX CPHY_v1.0 / DPHY_v1.2, 3-TRIO/1C4D, HLMC 55HR
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices.
USB1.1 build-in clock PHY, SMIC 55EF
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
USB1.1 build-in clock PHY, HLMC 40LP
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.