The QSPI master core is easy to use, simple to work with, quick to operate, and reliable under all conditions.
- SPI / QSPI XSPI
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The QSPI master core is easy to use, simple to work with, quick to operate, and reliable under all conditions.
ONFI 5.0 NAND Fash PHY IP Compliant to JEDEC
Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard.
ONFI 5.0 NAND Flash Controller IP Compliant to JEDEC
The NAND flash controller IP provides easy, reliable access to an off-chip NAND flash.
ONFI 4.2 NAND Flash Software Driver
The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it.
ONFI 4.2 NAND Flash Controller & PHY IP Compliant to JEDEC
The NAND Flash landscape is changing and the NAND Flash Controller IP Core is changing in accordance with it.
Classical CAN, also known as CAN 2.0 Bus Controller IP, is the foundational CAN bus standard.
The xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs.
Flow's Parallel Processing Unit solves one of computing's most fundamental dilemmas - parallel processing.
The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol.
The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol.
The MIPI® D-PHY RX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (D…
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
MIPI D-PHY/LVDS Combo Transmitter IP
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer…
Host Library for HDCP 2.3 on HDMI/DP Embedded Security Modules (generation 3)
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
HDCP 2 on HDMI / DisplayPort Embedded Security Module Firmware (generation 3)
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
1-port Receiver/Transmitter HDCP 2.3 on HDMI 2.0 or DisplayPort 1.4/2.0 ESM (generation 3)
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
HDCP Authentication Software Stack
The High-bandwidth Digital Content Protection (HDCP) Authentication Software Stack implements HDCP capability in a Trilinear Disp…