Decision tree ensemble evaluation core based on parallel evaluation of ensemble members
So_ip_edte_smpl_p core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consist…
- Edge AI Accelerator
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Decision tree ensemble evaluation core based on parallel evaluation of ensemble members
So_ip_edte_smpl_p core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consist…
Decision tree ensemble evaluation core based on serial evaluation of ensemble members
So_ip_edte_smpl_s core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consist…
Decision tree ensemble classifier inference core
So_ip_idte core can be used create an ensemble of decision trees directly in hardware.
Decision tree evaluation core using serial architecture
So_ip_edt_un core can be used to implement the decision tree with the previously defined structure directly in hardware.
Decision tree evaluation core using pipelined architecture
So_ip_edt_smpl core can be used to implement the decision tree with the previously defined structure directly in hardware.
Very High Speed 3GPP LTE Turbo Decoder
This is a very high speed and fully compatible 3GPP LTE turbo decoder with one, two, four or eight parallel MAP decoders.
Very High Speed 3GPP LTE Turbo Encoder
This is a very high speed 8 state 3GPP LTE compatible parallel concatenated turbo encoder.
High Speed CCSDS Turbo Encoder
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder.
The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard.
ATSC-M/H Mobile DTV Demodulator
The Santana core performs PHY layer demodulation and decoding for the ATSC M/H (A/153) mobile DTV standard, supporting all signal…
FireGate is a synthesizable IEEE-1394-2008 Beta PHY core and is architected to support data rates of S100 through S3200.
Viterbi decoder for 3GPP WCDMA and 3GPP-LTE
TC2000 is a flexible Viterbi decoder covering LTE, 3GPP WCDMA and WiMAX 16e/m specifications.
High Throughput Reed Solomon Decoder
This is a Reed Solomon decoder capable of operating with shortened codewords.
Mil-Std-1553B/AS15531 Interface
The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote …
High-Performance Lossless Compression/Encryption Combo Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from …
130nm FTP Non Volatile Memory for Standard CMOS Logic Process
NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot …
130nm OTP Non Volatile Memory for Standard CMOS Logic Process
NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot …
90nm FTP Non Volatile Memory for Standard CMOS Logic Process
NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot …
90nm OTP Non Volatile Memory for Standard CMOS Logic Process
NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot …
180nm FTP Non Volatile Memory for Standard CMOS Logic Process
NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot …