High-Performance Lossless Compression/Encryption Combo Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from …
Overview
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data.
LXP2 implements the lossless compression /decompression algorithm and AES-XTS encryption /decryption on units of data (“blocks”). Typical applications include enterprise data storage.
The design is fully synchronous and available in multiple configurations varying in bus widths and throughput.
LXP2 delivers 1-3 Gbps of throughput in both FPGA and ASIC implementations. The compression ratio greatly depends on the data and somewhat depends on the frames size; on typical file corpuses varies between 1.5 and 2.
Key features
- Each frame is compressed and decompressed independently
- Compatibility with public-domain LZ software implementations allows for interoperability
- Parameterizable maximum block size (up to 16 megabytes)
- Support for compression and decompression in a single core; dedicates compression and decompression versions are available
- Back-to-back compression with no gaps between the frames
Block Diagram
Applications
- High-performance solid-state storage
- Disk and tape storage systems
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Symmetric Cryptography IP cores
What is High-Performance Lossless Compression/Encryption Combo Core?
High-Performance Lossless Compression/Encryption Combo Core is a Symmetric Crypto IP core from IP Cores, Inc. listed on Semi IP Hub.
How should engineers evaluate this Symmetric Crypto?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.