Configurable Soft Output Demapper
Noesis Technologies Soft Output Demapper is a structural element of any modern telecom system.
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Configurable Soft Output Demapper
Noesis Technologies Soft Output Demapper is a structural element of any modern telecom system.
The RC4 core implements the RC4 stream cipher in compliance with the ARC4 specification.
The H264-MP-E core is an self-contained hardware H.264 encoder that conforms to the ITU-T H.264 Main Profile.
DVB-RCS and IEEE 802.16 WiMAX turbo encoder
This is an 8 state DVB-RCS and IEEE 802.16 WiMAX compatible parallel concatenated turbo encoder.
The so_ip_srio_ctrl is a soft core implementation of Serial RapidIO controller as defined in the RapidIO specification 2.2.
Supported Standards Decoder : AVC, MVC, MPEG-4, VC-1, MPEG-2, H.263, AVS Jizhun, AVS+ Guangdian, On2 VP8, Sorenson Spark, Theora …
Rambus MIPI Testbench from Rambus emulates a MIPI device enabling end-to-end simulation of a MIPI design.
The MIPI DSI-2 controller core is optimized for high performance, low power and small size.
The MIPI CSI-2 controller core is optimized for high performance, low power and small size.
The Rambus Mem Test Analyzer Core from Rambus is used to capture the results from Rambus Memory Test Core.
Embedded MTP (Multi-Time Programmable) IP,1x8 bits for 1.8V/5V/30V HV
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,1x32 bits for 1.8V/5V/30V HV
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,1x32 bits for 1.8V/5.5V LP
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,1x32 bits for 1.8V/5.5V/+-16V HV_GBG
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,1x32 bits for 1.8V/6V/30V HV
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,1x32 bits for 1.5V/5V/30V HV
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,1x32 bits for 1.8V/6V/30V HV
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,1x64 bits for 1.8V/5.5V/+-16V HV_GBG
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,32x16 bits for 1.8V/5.5V/32V HV_GBG
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,32x16 bits for 1.5V/5.5V/32V HV_GBG
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…