The GCE1-MP core implements Rijndael encoding and decoding in compliance with the NIST Encryption Standard and encryption/authent…
- Symmetric Crypto
- Now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The GCE1-MP core implements Rijndael encoding and decoding in compliance with the NIST Encryption Standard and encryption/authent…
The CMAC1 core provides implementation of cryptographic hashes AES-CMAC per NIST SP 800-38B and AES-XCBC.
Generic CCM AES Core with CMAC Option
The CCM2 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C.
Implementation of the new ITU G.9961 standard for home networking requires the NIST standard AES cipher in CTR and CBC modes (a.k…
Implementation of the WLAN security standard (802.11i) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a.
SHA1, SHA2 Cryptographic Hash Cores
The SHA cores provide implementation of cryptographic hashes SHA-1 (core SHA1), SHA-2 (cores SHA2-256 and SHA2-512).
HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol.
High-Performance Lossless Compression Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from …
SSL/TLS Processor IP Core with an AXI Bus Interface
The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites.
True Random and Pseudorandom Number Generator
The true random generator core implements true random number generation.
The CONV_YC IP Core is a fully pipelined chroma resampler that converts pixels between 4:4:4 and 4:2:2 formats in the YCbCr colou…
The CSC IP Core is a fully pipelined colour-space converter that converts pixels between the RGB and YCbCr colour spaces.
UART ,is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally, identical to the TL16C450.
USB2.0 Host controller using xHCI for High Performance
GDA’s USB 2.0 Host controller is a configurable core and implements the USB 2.0 Host functionality that can be interfaced with th…
Certified USB2.0 Device Controller
GDA’s USB 2.0 Device controller is a configurable core and implements the USB 2.0 Device functionality that can be interfaced wit…
100 dB of SNR, 24-bit multichannel audio CODEC with embedded regulator and high CMRR
Today s market for automotive infotainment applications has become a key challenge for car makers which require optimal vocal com…
USB 1.1/2.0 full speed USB PHY
T25201 is a and high integrated USB 2.0 low speed and full speed transceiver implementing the physical layer of a USB compliant d…
SATA 3 Host Controller on ZYNQ
The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA.
Aurora-like 64b/66b @14Gbps for ALTERA Devices
REFLEX CES introduces a release at 14Gbps of its Aurora-like IP Core based on ALTERA FPGA enabling interoperability between XILIN…
1024 State 3GPP2 Viterbi Decoder
The VA10V is a 1024 state error control decoder using the maximum likelihood Viterbi algorithm.