Overview
The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites.
SSL1-AXI has a “lookaside” interface to the rest of system through two AXI interfaces:
•AXI3/AXI4 slave for control
•AXI3/AXI4 master for data transfer
The data stream through the control interface contains processing commands. Each command consists a pointer to the descriptor in the system memory. Descriptor contains source, destination, encryption context, processing length, and status.
The encryption context (keys, encryption state, etc.) as well as the packets are stored in the system memory attached to the AXI bus and are read and written via the master interface.
The design is fully synchronous and is available in Verilog.
Learn more about IPsec / TLS IP core
Over the next five years, all security protocols and public key cryptography will undergo a comprehensive overhaul to ensure quantum safety. This represents the most significant change in these domains since the advent of public key cryptography.
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