12-bit 1-channel 20 to 100 MSPS ADC
The low-power high-speed 12-bit ADC employs a high-performance differential pipeline architecture.
- 12 Bit
- TSMC
- 65nm
- GP
- Silicon Proven
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12-bit 1-channel 20 to 100 MSPS ADC
The low-power high-speed 12-bit ADC employs a high-performance differential pipeline architecture.
12-bit 1-channel 4 MSPS SAR ADC
065TSMC_ADC_10 employs high-performance differential successive approximation architecture with sub-ranging and output offset com…
12-bit 4-channel 20 to 100 MSPS ADC
Quad-channel 12-bit 20 – 100 MSPS ADC contains four ADC channels, LVDS receiver, reference voltages and reference currents circui…
Multi-channel Audio Digital Interface (MADI) IP Core
The Verien Design Group MADI IP core is proven technology.
This device is designed to generate a quadrature heterodyne (oscillator) signal.
1.22 V Reference voltage source
Reference voltage source forms temperature-compensated voltage level equal to the width of the band gap of silicon due to mutual …
612.7 mV Reference voltage source
Reference voltage source forms temperature-compensated voltage level due to mutual compensation of temperature dependence of bipo…
1.19 V Reference voltage source
Reference voltage source forms temperature-compensated voltage level equal to the width of the band gap of silicon due to mutual …
Phase-locked loop system 2.8 to 3.3 GHz
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multip…
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
Variable FFT (run time choice of FFT size)
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
LTE Single Carrier FFT Circuit
Centar's DFT circuit can perform all 35 transform sizes needed to implement the LTE SC-FDMA protocols.
62.5MHz to 2GHz low jitter 1.2V supply PLL
The nSPLL_SIL130G_1V2 cell is a fully-programmable PLL IP cell powered at 1.2V ±10% designed on the Silterra 130 G technology.
The DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on FPGAs.
24.84 MHz phase-frequency detector with charge pump
The device consists of phase frequency detector (PFD), charge pump and lock detector (LD) PFD compares phases of a divided VCO si…
1 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_08 is LVDS receiver with rail to rail input range.
065TSMC_LVDS_07 is LVDS transmitter.
16-bit 2-channel 25 kHz bandwidth delta-sigma stereo, audio DAC
Delta-sigma stereo, audio DAC contains: reference voltage, control logic, digital buffers I2S interface (ws, sd, sck, gpio), two …
The 10-bit 100 MSPS ADC employs a high-performance front-end sample-and-hold with differential multi-stage pipelined architecture…
Library of LVDS IOs cells for TSMC 65LP
The nSIO2000_TS65LP_2V5_1V2 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.2V or…